Traffic signal control system

ABSTRACT

A system for controlling the traffic signals within a relatively wide district divided into a plurality of subdistricts, in each of which there are distributed many traffic signals at different places. A submaster controller coordinately controls many local controllers within each subdistrict, and a master controller controls all the submaster controllers within the wide district. The master controller gives the same cycle pulses and the same series of synchronizing pulses, but different offsets, to different submaster controllers, and each submaster controller provides a second series of synchronizing pulses, which are displaced in time from the first series of synchronizing pulses by the offset time given to the submaster controller, to the local controllers belonging to the submaster controller, so that the local controllers control their respective traffic signals on the basis of the synchronizing pulses received from the submaster controller. Thus, with proper different offsets given to the different submaster controllers, all the traffic signals in the wide district are coordinately controlled in accordance with the actual traffic conditions in the different subdistricts for establishment of smooth traffic flows throughout the wide district.

Mates Patnt mite Endo et al. [451 Mar. 2, 1972 [54] TRAFFIC SKGNALCONTROL SYSTEM I Primary ExaminerWilliam C. Cooper [72] Inventors E13:Endo Mituhisa Hosika Kyoto Att0rneyChristensen, Sanborn & Matthews [73]Assignee: Omron Tateisi Electronics Co., Ukyo-ku, CT

Kyoto Japan A system for controlling the traffic signals within arelatively 22] i 11, 1970 wide district divided into a plurality ofsubdistricts, in each of which there are distributed many trafficsignals at different [21] P 10,403 places. A submaster controllercoordinately controls many local controllers within each subdistrict,and a master con- Foreign Application Priority Data troller controls allthe submaster controllers within the wide district. The mastercontroller gives the same cycle pulses and Feb. 2 l, 1969 Japan..44/13442 the same series of synchronizing pulses, but differentoffsets, Mar. 8, 1969 Japan ..44/17685 to different submastercontrollers, and each submaster controller provides a second series ofsynchronizing pulses, which [52] U.S. Cl ..340/40, 340/ are displaced intime from the first series of synchronizing pul- [51] Int. Cl. ..G08g1/00 ses by the offset time given to the submaster controller, to the[58] Field of Search ..340/35 local controllers belonging to thesubmaster controller, so that the local controllers control theirrespective traffic signals on [5 6] References Cited the basis of thesynchronizing pulses received from the submaster controller. Thus, withproper different offsets given to UNITED STATES PATENTS the differentsubmaster controllers, all the traffic signals in the 3 305 828 2/1967Auor 340/ wide district are coordinately controlled in accordance withthe actual traffic conditions in the different subdistricts for3,363,185 1/1968 Sanderson et al ..340/40 establishment of Smooth nameflows throughout the wide dis FOREIGN PATENTS OR APPLICATIONS trici'1,187,054 4/1970 Great Britain ..340/35 4 Claims, 4 Drawing FiguresLUEAL 4 SUBMASTER m 7 EUNTRULLER m g fi 5TRAFFIC f itifitt MASTER 9EDNIRULLER WW 4 3 EUNTRULLER SUBMASTER LUCAL 7 ,J CONTROLLER CONTROLLERLOCAL /8 EUNIRULLER TRAFFIC INFURMAHUN DETEUUR PATENTED mes I972 SHEET 1OF 2 FIG. 1.

SUBMASTER MASTER CONTROLLER CONTROLLER LOCAL CONTROLLER LOCAL LOCALSUBMASTER CONTROLLER ANO ANO

ANO

CONTROLLER LOCAL CONTROLLER LOCAL TRATHC PULSE COUNTER CONTROLLER FIG.2.

TITIEIIT TRAFFIC REGISTER THHH COINCTOENCE CIRCUIT AND AND

AND

ANO

INVENTORS 72mm 0/ BY AVTV/Y/J! {MIA ATTORNEY! TRAFFIC SIGNAL CONTROLSYSTEM This invention relates to a system for controlling the trafficsignals within a relatively wide district.

There are known many systems which coordinately control many trafficsignals distributed over a wide district. Suppose that the trafficsignals within a certain area are coordinately controlled from a centralcontroller and that the traffic signals within a different area adjacentto the first-mentioned area are also coordinately controlled fromanother central controller. If there is no reaction existing between thetwo central controllers, it is highly probable that confusion shouldarise to the traffic especially near the border between the twoneighboring areas, thereby seriously impairing the effect of thecoordinated signal control within the individual areas.

Accordingly, it is one object of the invention to provide a system forcoordinately controlling the traffic signals in a wide district dividedinto a plurality of subdistricts for establishment of smooth trafficflows therebetween. Another object of the invention is to provide asystem for coordinately controlling the traffic signals in a widedistrict divided into a plurality of subdistricts, wherein there areprovided a plurality of submaster controllers each for one of thesubdistricts to coordinately control a plurality of local controllersdirectly controlling their respective traffic signals within thesubdistrict, and wherein there is further provided a single mastercontroller to coordinately control the submaster controllers forestablishment of smooth traffic flows between the subdistricts.

In accordance with the invention, a relatively wide district withinwhich the traffic signals are to be controlled is divided into aplurality of subdistricts, for each of which a submaster controller isprovided to coordinately control many local controllers within thesubdistrict. Each local controller controls the traffic signalsbelonging to it. A single master controller is provided to control allthe submaster controllers within the wide district. The mastercontroller gives the same cycle pulses and series of synchronizingpulses to all the submaster controllers. For coordinate control of thetraffic signals between neighboring subdistricts, however, the mastercontroller gives different offsets to different submaster controllers inneighboring subdistricts. Each submaster controller provides a secondseries of synchronizing pulses, which are displaced in time from thefirst series of synchronizing pulses by the offset time given to thesubmaster controller, to the local controllers belonging to thesubmaster controller, so that on the basis of these synchronizing pulseseach local controller controls its own traffic signals. Thus, withsuitable offsets given to different subdistricts, the traffic signalswithin the wide district can be coordinately controlled in accordancewith the actual traffic conditions in the individual subdistricts.

The invention will be better understood from the following descriptionof a preferred embodiment thereof with reference to the accompanyingdrawing, wherein;

FIG. I is a general layout of the system of the invention shown as anelectrical block diagram;

FIG. 2 is a detailed electrical block diagram of the submastercontroller used in the system;

FIG. 3 is a time chart of the various signals in the circuit of FIG. 2for explanation of the operation thereof; and

FIG. 4 is a diagram similar to FIG. 2 but showing a modified form of thesubmaster controller.

In the embodiment of FIG. 1, it is assumed that the system covers twosubdistricts, although in practice as many submaster controllers as arerequired may be controlled by a single master controller in a similarmanner. One of the two subdistricts includes two local controllers 4 and5, and the other, three local controllers 6, 7 and 8. As many localcontrollers as are required may be provided in each subdistrict. Asubmaster controller 2 is provided to control the local controllers 4and 5; and a second submaster controller 3, to control the localcontrollers 6, 7 and 8. In practice, for example, the whole district ofa city may be divided into as many subdistricts as are required so thata submaster controller is provided for each subdistrict to control thelocal controllers distributed at different places within thesubdistrict.

In each subdistrict, a traffic information detector 9, I0 is provided todetect the present traffic conditions in the subdistrict. The submastercontroller 2 coordinately controls the local controllers 4 and 5, withthe splits and offsets as determined by the submaster controller on thebasis of the traffic information received from the detector 9; and thesubmaster controller 3 coordinately controls the local controllers 6, 7and 8, with their splits and offsets as determined by the submastercontroller 3 on the basis of the traffic information received from thedetector 10.

The submaster controllers 2 and 3 transmit the traffic informationsreceived from the detectors 9 and 10, respectively, to a single mastercontroller 1, which determines the signal cycle of all the trafficsignals in the system and the offsets of the submaster controllers 2 and3.

When the master controller has determined the signal cycle, it producescorresponding pulses (to be referred to as cycle pulses) having afrequency inversely proportional to the cycle length. The submastercontrollers operate on the basis of the cycle pulses received from themaster controller, as will be described later, and at the same timetransmit the cycle pulses to the local controllers 4, 5, 6, 7 and 8.

Besides the cycle pulses, the master controller ll transmits to thesubmaster controllers those pulses which are in synchronism with eachsignal cycle (to be referred to as SMC synchronizing pulses), on thebasis of which the submaster controllers operate, as will be describedlater in detail. The master controller also transmits to the submastercontrollers the signals (to be referred to as SMC offset signals") whichcommand different offsets to be taken by different submastercontrollers. The submaster controller 2 produces those synchronizingpulses (to be referred to as LC synchronizing pulses") from which theSMC synchronizing pulses are displaced by the ofiset time taken by thesubmaster controller 2 and applies the LC synchronizing pulses to thelocal controllers 4 and 5; and the submaster controller 3 produces LCsynchronizing pulses from which the SMC synchronizing pulses aredisplaced by the different offset time taken by the submaster controller3 and applies these LC synchronizing pulses to the local controllers 68. Thus, the local controllers 4 and 5 in the first subdistrict and thelocal controllers 6 8 in the second subdistrict are controlled not bythe same synchronizing pulses but by the synchronizing pulses displacedfrom the SMC synchronizing pulses to different degrees, so that thetraffic signals in the first and second subdistricts are coordinatelycontrolled.

FIG. 2 shows the details of the arrangement of each submaster controllerof FIG. 1. The master controller applies cycle pulses of differentfrequencies to three terminals C1, C2 and C3. In the following pages,the line or terminal and the signal thereon will sometimes be referredto by the same reference numeral. The signal Cl has a frequency of I00pulses per signal cycle; the signal C2, a lower frequency of 100 pulsesper 1.25 signal cycle; and the signal C3, a higher frequency of 100pulses per 0.875 signal cycle. The signals C1, C2 and C3 are applied asone input to AND elements ll, 12 and 13, respectively. A tri-stablecircuit 25 applies its three outputs B1, B2 and B3 as the other input tothe AND elements 1 1, 12 and 13, respectively, as will be described indetail later.

The output pulses from the AND elements 11 13 are applied through an ORelement 14 to a pulse counter 15. The counter is so designed thatwhenever it has counted the 100th pulse applied thereto, it is returnedto zero and at the same time produces an output on a line S00; and thatwhen four, 50 and pulses have been counted, it produces an output onlines S04, S50 and 590, respectively. In other words, as the counter 15steps forward, it produces an output on the lines S00, S04, S58 and S90upon lapse of times equal to 0 percent, 4 percent, 50 percent and 90percent of one signal cycle length, respectively. These output signalsare used as the LC synchronizing signals to be applied to the localcontrollers belonging to the submaster controller.

The SMC offset signal provided by the master controller is applied to aterminal S0 in the form of binary decimal code.

The coded signal S is stored in a 7-bit register 16 which is capable ofstoring decimal numbers up to 100. The previously mentioned counter 15is of a construction similar to the register 16 and has seven outputlines. The outputs corresponding to the 7 bits of the register 16 areapplied to a coincidence circuit 17, to which the seven outputs from thecounter 15 are also applied. The circuit 17 compares the value stored inthe register 16 and the counted value on the counter 15 and produces anoutput on a line OS when the two values coincide, This signal OS isapplied as one input to four AND elements 21 to 24.

The master controller also applies the SMC synchronizing pulses toterminals M011, M04, M50 and M90. The signal M00 is a pulse producedupon lapse of every one signal cycle, and the signals M0 1, M511 and M90are pulses produced upon lapse of 4 percent, 50 percent and 90 percentof every one signal cycle, respectively, after the production of thesignal M011. These signals M110 M90 are shown in FIG. 3 (a) (e),respectively.

The signal M1141 is applied as a set input to a flip-flop 18, to whichthe signal M90 is applied as a reset input. Therefore, the flip-flop 18is kept set during the period of time from 4 percent to 90 percent ofone signal cycle length. The set and reset outputs from the flip-flop 18are shown in FIG. 3 (f) and (g), respectively. The signal M50 is appliedas a set input to a flipflop 19, to which the signal M00 is applied as areset input. Therefore, the flip-flop 19 is kept set during the periodof time from 50 percent to 100 percent of one signal cycle. The set andreset outputs from the flip-flop 19 are shown in FIG. 3 (h) and (i),respectively.

The set output from the flip-flop 18 is applied as a second input to theAND element 21, to which the set output from the flip-flop 19 is appliedas the third input. Therefore, as shown in FIG. 3 (i), the AND element21 produces an output only when the signal 08 is produced by thecoincidence circuit 17 during the period oftime from 50 percent to 90percent ofone signal cycle length. In the following description,expressions such as the period of time from 50 percent to 90 percent ofone signal cycle length" will be expressed simply as the 50 90 percentperiod of time. The reset output from the flip-flop 18 is applied as theother input to the AND element 22. Therefore, as seen from FIG. 3 (k)the element 22 produces an output only when the signal 08 is producedduring the 90 100 percent period of time, or the O 4 percent period oftime of one signal cycle. The set output from the flip-flop 18 isapplied as a second input to the AND element 23, to which the resetoutput from the flip-flop 19 is applied as the third input. Therefore,as seen from FIG. 3 (I) the AND element 23 produces an output only whenthe signal is produced during the 4 50 percent period of time of onesignal cycle. Finally, the reset output the flip-flop 18 is applied as asecond input to the AND element 24, to which the set output from theflip-flop 19 is applied as the third input. Therefore, as seen from FIG.3 (m) the AND element 24 produces an output only when the signal 118 isproduced during the 90 100 percent period of time of one signal cycle.

The outputs from the AND elements 21 23 are applied as three inputs tothe tri-stable circuit 25. When the output from the AND element 21 isapplied as an input F to the circuit 25, it produces an output on a lineB1; when the output from the AND element 22 is applied as an input S tothe circuit 25, it produces an output on a line B2; and when the outputfrom the AND element 23 is applied as an input T to the circuit 25, itproduces an output on a line B3. Let it be assumed that in FIG. 2 theinput S is applied to the circuit 25, which produces an output on theline B2.

The output ST from the AND element 24 is applied as one input to the ORelement 14. Therefore, so long as the output ST continues to be appliedthrough the OR element 14 to the counter 15, the counter does not stepforward even when any of the AND elements 11 13 applies pulses to thecounter 15.

Suppose that on the basis of the traffic informations received from thedetectors 9 and 10, the master controller has decided that is necessaryto change the offsets in the subdistricts, and accordingly applies thesignal SO expressing a new offset to the register 16 of the submastercontroller 2 or 3 to be stored therein. At this time the counter 15 isstepping forward due to the normal cycle pulses C2 applied theretothrough the AND element 12 and the OR element 14. When the counter 15has reached the count which coincides with the new offset value storedin the register 16, the coincidence circuit 17 produces an output on theline 05, as previously mentioned. Naturally, the synchronizing relationbetween the signal OS and the SMC synchronizing pulses being applied tothe terminals M04, M50, M and M01) now becomes different from thatbefore the new offset has been stored in the register 16.

Suppose that the signal OS has been produced during the 50 90 percentperiod of time of the signal cycle. The moment the signal 05 has beenproduced, the AND element 21 produces an output to be applied as theinput F to the tri-stable circuit 25, so that the output B1 is producedto be applied to the AND element 11. Then, the counter 15 begins tocount the cycle pulses applied thereto through the terminal C1. Sincethe frequency of these pulses C1 is lower by 12.5 percent than that ofthe standard cycle pulses C2, the time required for the counter 15 tocount pulses applied through the terminal C1 becomes 12.5 percent longerthan the time required for the counter to count 100 pulses appliedthrough the terminal C2. In other words, one signal cycle length has nowbecome 12.5 percent longer than the normal signal cycle length. It willbe easily seen that as this lengthened signal cycle is repeated three orfour times at most, the signal OS comes to appear within the 90 1111)percent or 0 4 percent period of time of the normal signal cycle lengthas defined by the SMC synchronizing pulses applied to the terminals M011M90,

in case the signal OS has appeared within the 90 100 percent period oftime, the AND element 24 produces an output on the line ST to be appliedthrough the OR element 14 to the counter 15. So long as this signal STis being applied to the counter 15, it does not progress. During the 90100 percent period of time, the AND element 22 produces an output sothat the output B2 from the circuit 25 is applied to the AND element 12.This causes the pulses C2 to be applied through the AND element 12 andthe OR element 14 to the counter 15. However, the continuous applicationof the signal ST to the counter 15 prevents the pulses C2 fromprogressing the counter 15. When the 90 100 percent period of time haselapsed, however, the signal M1111 causes the signal ST to disappear,whereupon the counter 15 begins counting the cycle pulses C2. Since 100pulses C2 are produced for every one normal cycle length, the counter 15is returned to zero count upon lapse of every one normal cycle. Thus,the discrepancy between the SMC synchronizing pulse M and the LCsynchronizing pulse S111) becomes equal to the new offset as stored inthe register 16. From this time on the counter 15 produces LCsynchronizing pulses on the basis of the new offset until the offset isagain changed.

In case the signal ST has appeared within the 0 4 percent period oftime, the AND element 22 produces an output on the line 132, whereuponthe counter 15 begins counting pulses C2.

Suppose that the signal OS from the coincidence circuit 17 is producedwithin the 4 50 percent period of time of the signal cycle. Then, theAND element 23 produces an output to be applied to the input T of thetri-stable circuit 25, so that the circuit 25 produces an output on theline 133 to be applied to the AND element 13. This causes the counter 15to count the cycle pulses C3 applied thereto through the OR element 14.Since the frequency of the pulses C3 is higher by 12.5 percent than thatof the normal pulses C2, the time required for the counter 15 to count100 pulses C3 becomes shorter by 12.5 percent than the normal signalcycle length. Therefore, while the shortened signal cycle is repeatedthree times at most, the signal OS comes to appear within the 0 4percent period of time of the signal cycle as defined by the SMCsynchronizing pulses, or while the shortened signal cycle is repeatedfour times at most, the signal OS comes to appear within the 90 100percent period of time of the normal signal cycle. Then the output $00from the counter is forwardly displaced from the signal M00 by the newoffset as stored in the register 16. In other words, the counter 15 nowproduces LC synchronizing signals on the basis of the new offset.

The LC synchronizing signals, that is, S00, S04, S50 and S90 aretransmitted to the local controllers belonging to the submastercontroller. The submaster controller determines an offset for each ofthe local controllers. On the basis of the offset and the LCsynchronizing signals received from the submaster controller, each localcontroller provides its own synchronizing signals to control the trafficsignals belonging to it in a manner so well known in the art that noexplanation thereof will be given.

FIG. 4 shows a modified form of the submaster controller shown in FIG.2. Here, the register 16 and the coincidence circuit 17 in FIG. 2 arereplaced by a circuit including a reversible register. in FIG. 4 thecomponent parts corresponding to those in FIG. 2 are designated by thesame reference numerals, and the following description will be limitedto those portions which differ from the arrangement of FIG. 2.

The master controller applies an offset signal to a terminal SO. As inthe case of FIG. 2, the signal S0 is in the form of binary decimal code.Simultaneously with the application of the signal SO, the mastercontroller also applies another signal to a terminal SOC. This signalSOC is a continuous signal unlike the signal S0. The two signals SO andSOC are applied to an AND element 32, so that the signal S0 is appliedthrough an OR element 34 to a reversible register 35 having a capacityof storing decimal numbers up to 100. Thus, the new offset valuetransmitted as the signal SO from the master controller is stored in theregister 35. The register 35 is capable of storing the signal SO onlywhile the signal SOC is being applied thereto as a continuous inputthrough a line SRC. If the pulses from the OR element 34 are applied tothe register 35 without the control input SRC, the register 35 subtractsa value corresponding to the pulses applied from the OR element 34(which will be referred to as subtraction pulses") from the value storedin the register 35 until the stored value is reduced to zero, whereuponthe register 35 produces a signal on a line OS. After that time, if theOR element 34 further applies subtraction pulses to the register 35, theregister 35 subtracts the applied subtraction pulses from 100.

The output signal OS from the register 35 is applied as one input to theAND elements 21 24 just as in the case of FIG. 2. The subtraction pulsesapplied to the register 35 are the pulses applied thereto from the ORelement 14 through an AND element 33 and the OR element 34. .A flip-flop31 applies its reset output to one input of the AND element 33. Thepreviously mentioned signal SOC is applied as a set input to theflipflop 31, to which the output $00 from the counter 15 is applied as areset input. Therefore, so long as the signal SOC exists, the ANDelement 33 produces no output, and when the signal 800 has appeared, theregister 35 receives subtraction pulses to be subtracted from the valuestored in the register 35. Thus, when after the production of the signal800, the

new offset value stored in the register 35 has been reduced to zero,that is, when the new offset time as selected by the master controllerhas passed, the signal OS is produced. The operation of the embodimentof FIG. 4 will be so easily understood from the previous explanation ofFIG. 2 that no further description will be required.

What we claim is:

l. A system for controlling the traffic signals within a wide districtdivided into a plurality of subdistricts, comprising: a plurality oflocal controllers to control the traffic signals provided at differentplaces in each of said subdistricts, a submaster controller provided foreach of said subdistricts for controlling said local controllers withineach said subdistrict;

and a single master controller for controlling said submastercontrollers and including means for providing cycle pulses and a firstseries of synchronizing pulses to be applied to all said submastercontrollers and means for providing a different offset signal to beapplied to each of said submaster controllers; each said submastercontroller including means for providing a second series ofsynchronizing pulses displaced from said first-mentioned series ofsynchronizing pulses by the offset time as determined by said offsetsignal, and means for applying said second series of synchronizingpulses to each said local controller, whereby each said local controllercontrols the trafiic signals belonging thereto on the basis of saidsecond series of synchronizing pulses received from each said submastercontroller.

2. The system of claim 1, wherein each said submaster controllerincludes a register for storing said offset signal received from saidmaster controller, a counter for counting said cycle pulses receivedfrom said master controller to produce said second series ofsynchronizing pulses as predetermined counts are reached, and circuitmeans for controlling said counter so that the time between theoccurrence of said first and second series of synchronizing pulsesbecomes equal to said offset stored in said register.

3. The system of claim 1, wherein said submaster controller comprises aregister for storing said offset signal, a counter for counting saidcycle pulses to produce said second series of synchronizing pulses aspredetermined counts are reached, a coincidence circuit operable toproduce an output when the count on said counter has come to coincidewith said offset stored in said register, means for detecting adiscrepancy in occurrence between said output from said coincidencecircuit and a first pulse in said first series of synchronizing pulsesto produce an output, and means operable in response to said output fromsaid detecting means to change the frequency of said cycle pulses to beapplied to said counter.

4. The system of claim 1, wherein each said submaster controllercomprises a first counter for counting said cycle pulses, a register forstoring said offset signal, said register also receiving said cyclepulses to function as a second counter having the same counting capacityas said first counter to produce a signal when a predetermined count hasbeen reached, means for detecting a discrepancy in occurrence betweensaid signal from said second counter and a first pulse in said firstseries of synchronizing pulses to produce an output, and means operablein response to said last-mentioned output to change the frequency ofsaid cycle pulses to be applied to said first counter.

1. A system for controlling the traffic signals within a wide districtdivided into a plurality of subdistricts, comprising: a plurality oflocal controllers to control the traffic signals proVided at differentplaces in each of said subdistricts, a submaster controller provided foreach of said subdistricts for controlling said local controllers withineach said subdistrict; and a single master controller for controllingsaid submaster controllers and including means for providing cyclepulses and a first series of synchronizing pulses to be applied to allsaid submaster controllers and means for providing a different offsetsignal to be applied to each of said submaster controllers; each saidsubmaster controller includ-ing means for providing a second series ofsynchronizing pulses displaced from said firstmentioned series ofsynchronizing pulses by the offset time as determined by said offsetsignal, and means for applying said second series of synchronizingpulses to each said local controller, whereby each said local controllercontrols the traffic signals belonging thereto on the basis of saidsecond series of synchronizing pulses received from each said submastercontroller.
 2. The system of claim 1, wherein each said submastercontroller includes a register for storing said offset signal receivedfrom said master controller, a counter for counting said cycle pulsesreceived from said master controller to produce said second series ofsynchronizing pulses as predetermined counts are reached, and circuitmeans for controlling said counter so that the time between theoccurrence of said first and second series of synchronizing pulsesbecomes equal to said offset stored in said register.
 3. The system ofclaim 1, wherein said submaster controller comprises a register forstoring said offset signal, a counter for counting said cycle pulses toproduce said second series of synchronizing pulses as predeterminedcounts are reached, a coincidence circuit operable to produce an outputwhen the count on said counter has come to coincide with said offsetstored in said register, means for detecting a discrepancy in occurrencebetween said output from said coincidence circuit and a first pulse insaid first series of synchronizing pulses to produce an output, andmeans operable in response to said output from said detecting means tochange the frequency of said cycle pulses to be applied to said counter.4. The system of claim 1, wherein each said submaster controllercomprises a first counter for counting said cycle pulses, a register forstoring said offset signal, said register also receiving said cyclepulses to function as a second counter having the same counting capacityas said first counter to produce a signal when a predetermined count hasbeen reached, means for detecting a discrepancy in occurrence betweensaid signal from said second counter and a first pulse in said firstseries of synchronizing pulses to produce an output, and means operablein response to said last-mentioned output to change the frequency ofsaid cycle pulses to be applied to said first counter.